Difference between revisions of "FPGA"

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As of August 2022, Grid'5000 features 2 nodes, each equipped with one AMD/Xilinx FPGA.
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As of August 2022, Grid'5000 features 2 nodes, each equipped with one AMD/Xilinx FPGA. This document gives specific information related to how those FPGA are usable in Grid'5000.
 
[[File:AMD Xilinx Alveo U200.jpg|thumb|right|AMD Xilinx Alveo U200]]
 
[[File:AMD Xilinx Alveo U200.jpg|thumb|right|AMD Xilinx Alveo U200]]
  

Revision as of 15:39, 2 September 2022

As of August 2022, Grid'5000 features 2 nodes, each equipped with one AMD/Xilinx FPGA. This document gives specific information related to how those FPGA are usable in Grid'5000.

AMD Xilinx Alveo U200

Hardware description

The Grenoble site of Grid'5000 hosts 2 servers (Servan cluster) equipped with an AMD/Xilinx FPGA. FPGA are AMD/Xilinx Alveo U200, which are PCIe Accelerator card.

Detailed specifications are provided here (cards with passive thermal cooling).

Technically, the installation of those FPGAs in the Servan nodes has the following characteristics:

  • JTAG
    • JTAG programming is provided on Xilinx Alveo U200 via a USB port on the card. In the Grid'5000 installation, it is cabled back to the hosting machine itself. Thus, programming of the FPGA of e.g. servan-1 can be done (e.g. with Vivado) from e.g. servan-1 itself.
  • Network
    • Both Ethernet ports of the FPGA are cabled to the site network along with all servers of the site (including the servan server NICs).
      Grenoble site network
    • Ethernet ports are not shown as NICs in the operating system of the hosting machine (unless FPGA is programmed as to do so).
    • Ethernet ports are cabled to 100Gbps ports on Grenoble site router/switch. Switch ports are configured with Auto-Negotiation disabled and Speed forced to 100Gbps (not working otherwise, as far as we tested).
    • Kavlan is supported on the FPGA Ethernet ports just like any NIC of a server of the site (including the servan servers NICs). FPGA ports are named servan-1-fpga0, servan-1-fpga1, servan-2-fpga0, servan-2-fpga1 in kavlan. IP addresses are provided via DHCP to the FPGA ports in kavlan where the DHCP service is available.
    • Note: using the 100Gbps capability of the FPGA ports requires acquiring a free-of-charge Xilinx licence.
  • Wattmeter
    • Each servan node energy consumption is measured by a wattmeter. Measures are available in Kwollect. (Work-in-progress)
    • Energy consumption can also be retrieved using Xilinx tools (e.g. xbutil, xbtop) from the host operating system when the FPGA is running XRT (see below).

Using the FPGA

Programming

FPGA can be used in serval ways:

  • either using higher-level abstractions, e.g. using Xilinx's Vitis.
  • or using lower-level abstractions, e.g. using Xilinx's Vivado.

When used with the higher level abstractions with Vitis, the FPGA card is managed by the XRT framework, and the card shows as a datacenter accelerator card. However, it is sometimes necessary to program the card at a lower level, such as for instance becoming a network card (NIC). In such a case, the card is fully reprogrammed, so that even its PCI id changes. Hence users have to decide at what level they want to program the FPGA.

Regarding the programming of the operations of the FPGA (typically with Vivado), several options are also available:

  • Via PCI-e.
    • PCI-e programming may not be available as it requires the FPGA to possibly already operate PCI-e support for programming.
  • Via JTAG, by flashing the program on the board-embedded non-volatile memory that lives beside the FPGA.
    • Flashing the non-volatile memory requires a cold reboot of the hosting server to make the FPGA utilize the flashed program. It makes the programming persistent, which means flashing a factory golden image will be required to revert the FPGA to its original operating mode.
  • Via JTAG, directly in the FPGA's volatile memory.
    • By programming the volatile memory, the FPGA will run the program straight away. A warm reboot may be required to make a program (e.g. if modifying the PCI-e) functional. A cold reboot will revert the FPGA to run the program installed in the non-volatile memory of the board.

As a result, it is recommended to prefer programming the FPGA via the volatile memory, so that the new programming is NOT persistent, and the FPGA returns back to its default operating mode after a cold reboot, typically after the reservation/job.

FPGA software stack

The servan nodes just like all Grid'5000 nodes are running Debian by default. No support is provided in that default operating system environment.

AMD/Xilinx supports a limited list of OS to operate the FPGA, see here. A kadeploy Ubuntu 20.04 image is provided by Pierre Neyron, which includes the Xilinx tools. Anyone may deploy it using:

kadeploy -u pneyron -e ubuntu2004-fpga

That ubuntu2004-fpga system environment is built using a kameleon recipe available in https://gitlab.inria.fr/neyron/ubuntu2004-fpga.

Vitis and Vivado are installed on a NFS shared storage (/tools/ in the deployed Ubuntu system), which access can be requested to Pierre Neyron.

Developping code for the FPGA

Getting help on how to code a program for the FPGA is out of the scope of this document.